"Gen-Z Ver.1.1" that supports 3 types of connection, booting from DRAM is not possible

I've talked about OpenCAPI twice in a row, but this time I want to get back to Gen-Z. Originally, Gen-Z considered the connection of DRAM from the beginning, as introduced in this article, and in fact, in 2016, a white paper called "Gen-Z + DDR: A winning combination" was also issued. In this, the idea of ​​connecting multiple DDR memories via Gen-Z is shown.

The difference from the OMI (Open Memory Interface) of "OpenCAPI 3.1" introduced last time is whether the memory controller is in front of the interconnect, that is, on the processor side, or ahead (that is, on the DRAM side). That's the point. In OMI, it will be placed on the processor side, and in Gen-Z, it will be placed on the DRAM side.

Which one is better depends on the implementation, but OpenCAPI was still in the 3.0 stage, and at this point it couldn't handle DRAM in the first place. In that connection, it is a situation that has to rely on a transitional solution like OMI, and in that case the memory controller has to be placed on the processor side.

On the other hand, Gen-Z had already realized memory sharing at the stage of Interconnect for HPC using InfiniBand. For example, when connecting host A and host B with InfiniBand, node A and node B each have a shared memory area, and when data is written to one side, it is immediately reflected on the other side. is.

If you use this with MPI, you can synchronize programs between multiple nodes. At this stage, InfiniBand supports the configuration of placing the memory controller ahead of the processor, so naturally Gen-Z will take over this as well.

That's why it's possible to do the same with Gen-Z, albeit in a different way than CAPI 3.1. Connectors also support DRAM connection from the beginning (or rather, unlike OpenCAPI, the interface is standardized in the first place, so there is no need to define another connector), so in theory it can be used without problems.